名額
70
已選
24
餘額
46
登記 1 人 · 選上機率 99.9%
上課時間
三/10,11,12[C108]
修課班級
資工系資電組3,4 · 年級以上
課程資訊
限資電組重修同學
選課分析
| Homework | 30 | |
| Midterm exams | 30 | |
| Final exam | 25 | |
| Attendance and participation | 15 |
This course is an extension of Digital Systems. A logical progression of Verilog HDL-based topics will be introduced.
1. Understanding advanced Verilog HDL. 2. Use Verilog HDL to design and simulate digital systems.
1. Verilog HDL, 2nd ed, Samir Palnitkar, SunSoft Press, 2003.
2. Digital Design, 5th ed. by M. Mano Prentice-Hall.
3. Advanced Digital Design with the Verilog HDL, 2nd ed, Michael D. Ciletti, Peasrson, 2010.
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