108年第2學期-1047 硬體描述語言 課程資訊

評分方式

評分項目	配分比例	說明
Homework	30
Midterm exams	30
Final exam	25
Attendance and participation	15

教育目標

1. Understanding advanced Verilog HDL. 2. Use Verilog HDL to design and simulate digital systems.

課程概述

This course is an extension of Digital Systems. A logical progression of Verilog HDL-based topics will be introduced.

基本資料

選修課，學分數：0-3
上課時間：二/7,8,9[ST436]
修課班級：資工系2-4
修課年級：年級以上
選課備註：限重修生、轉系生、轉學生、輔系及雙主修選課

參考書目

1. Verilog HDL, 2nd ed, Samir Palnitkar, Prentice Hall, 2003
2. Digital Design, 6th ed. by M. Mano Prentice-Hall, 2018
3. Advanced Digital Design with the Verilog HDL, 2nd ed, Michael D. Ciletti, Pearson, 2010.
4. Verilog 硬體描述語言 (Verilog HDL: A Guide to Digital Design and Synthesis, 2/e), 黃英叡、黃稚存, 全華, 2005