本課程已於 2018-03-07停開
名額
70
已選
8
餘額
62
上課時間
二/6,7,8[ST338]
修課班級
資工系2-4 · 年級以上
課程資訊
資電組分組選修
選課分析
1. Understanding Verilog HDL. 2. Able to analyze and design complex digital systems.
1. Digital Design An Embedded Systems Approach Using Verilog, Peter Ashenden, 2008 (Morgan Kaufmann)
2. Digital Systems Principles and Applications 10th ed., Tocci, 2007 (Pearson)
3. Fundamentals of Digital Logic with Verilog Design, 2nd ed., S. Brown and Z. Vranesic, 2008 (Mc Graw Hill)
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