110年第1學期-1026 硬體描述語言 課程資訊

評分方式

評分項目 配分比例 說明
Homework 30
Midterm exams 25
Final exam 25
Attendance and participation 20

選課分析

本課程名額為 70人,已有60 人選讀,尚餘名額10人。


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授課教師

劉榮春

教育目標

1. Understanding basic Verilog topics: gate-level modeling,data flow modeling and behavioral modeling. 2. Studying advanced topics such as timing simulation, switch-level modeling, UDPs, PLI, logic synthesis, and advanced verification techniques. 3. Use Verilog HDL to design and simulate digital systems.

課程概述

This course is an extension of Digital Systems. A logical progression of Verilog HDL-based topics will be introduced.

課程資訊

參考書目

1. Verilog HDL, 2nd ed, Samir Palnitkar, Prentice Hall, 2003
2. Digital Design, 6th ed. by M. Mano Prentice-Hall, 2018
3. Advanced Digital Design with the Verilog HDL, 2nd ed, Michael D. Ciletti, Pearson, 2010.
4. Verilog 硬體描述語言 (Verilog HDL: A Guide to Digital Design and Synthesis, 2/e), 黃英叡、黃稚存, 全華, 2005

開課紀錄

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