113年第1學期-1016 硬體描述語言 課程資訊

評分方式

評分項目	配分比例	說明
小考	25
Midterm exams	25
Final exam	25
homework and participation	15
補救教學(彈性學習週)	10

教育目標

1. Understanding basic Verilog topics: gate-level modeling,data flow modeling and behavioral modeling. 2. Studying advanced topics such as timing simulation, switch-level modeling, UDPs, PLI, logic synthesis, and advanced verification techniques. 3. Use Verilog HDL to design and simulate digital systems.

基本資料

選修課，學分數：3-0
上課時間：五/6,7,8[ST436]
修課班級：資工系2-4
修課年級：2年級以上
選課備註：資電工程學群課程

參考書目

1. Verilog HDL, 2nd ed, Samir Palnitkar, Prentice Hall, 2003
2. Digital Design, 6th ed. by M. Mano Prentice-Hall, 2018
3. Advanced Digital Design with the Verilog HDL, 2nd ed, Michael D. Ciletti, Pearson, 2010.
4. Verilog 硬體描述語言 (Verilog HDL: A Guide to Digital Design and Synthesis, 2/e), 黃英叡、黃稚存, 全華, 2005